Ð þíPA8Jè(YJ°,radxa,rockrockchip,rk3188 7Radxa Rockchosenaliases=/ethernet@10204000G/i2c@2002d000L/i2c@2002f000Q/i2c@20056000V/i2c@2005a000[/i2c@2005e000`/dwmmc@1021c000f/dwmmc@10214000l/dwmmc@10218000r/serial@10124000z/serial@10126000‚/serial@20064000Š/serial@20068000’/spi@20070000—/spi@20074000memoryœmemory¨`€amba ,simple-bus¬dma-controller@20018000,arm,pl330arm,primecell¨ €@³¾ÉäÀ ëapb_pclk÷/ý/dma-controller@2001c000,arm,pl330arm,primecell¨ À@³¾ÉäÀ ëapb_pclk disableddma-controller@20078000,arm,pl330arm,primecell¨ €@³¾ÉäÁ ëapb_pclk÷#ý#oscillator ,fixed-clock n6)xin24ml2-cache-controller@10138000,arm,pl310-cache¨€<J÷,ý,scu@1013c000,arm,cortex-a9-scu¨Àglobal-timer@1013c200,arm,cortex-a9-global-timer¨  ³ älocal-timer@1013c600,arm,cortex-a9-twd-timer¨Æ  ³ äinterrupt-controller@1013d000,arm,cortex-a9-gicVk¨ÐÁ÷ýserial@10124000,snps,dw-apb-uart¨@ ³"|†ëbaudclkapb_pclkä@Lokay“default¡serial@10126000,snps,dw-apb-uart¨` ³#|†ëbaudclkapb_pclkäAMokay“default¡usb@10180000,rockchip,rk3066-usbsnps,dwc2¨ ³äÃëotg«otg³ÅÔ€€@@ ãí òusb2-phyokayusb@101c0000 ,snps,dwc2¨ ³äÉëotg«hostí òusb2-phyokayethernet@10204000,rockchip,rk3188-emac¨ @< ³üäÄD ëhclkmacref drmiiokay“default ¡   ethernet-phy@0¨ ³÷ ý dwmmc@10214000,rockchip,rk2928-dw-mshc¨!@ ³äÀHëbiuciu+okay6“default¡@LVhydwmmc@10218000,rockchip,rk2928-dw-mshc¨!€ ³äÁIëbiuciu+ disableddwmmc@1021c000,rockchip,rk2928-dw-mshc¨!À ³äÂJëbiuciu+ disabledpmu@20004000,rockchip,rk3066-pmusyscon¨ @÷1ý1grf@20008000,syscon¨ €÷ýi2c@2002d000,rockchip,rk3188-i2c¨ Ð ³(üëi2cäP disabled“default¡i2c@2002f000,rockchip,rk3188-i2c¨ ð ³)üäQëi2cokay“default¡ €rtc@51,haoyu,hym8563¨Q³ “default¡)xin32kact8846@5a,active-semi,act8846¨Zokay„“default¡œ§²½ÈÔàregulatorsREG1ìVCC_DDRûO€O€+REG2ìVDD_LOGûB@B@+REG3ìVDD_ARMû Yø™p+÷-ý-REG4ìVCC_IOû2Z 2Z +÷ýREG5ìVDD_10ûB@B@+REG6 ìVDD_HDMIû&% &% +REG7ìVCC_18ûw@w@+REG8ìVCCA_33û2Z 2Z +REG9 ìVCC_RMIIû2Z 2Z ÷ ý REG10 ìVCCIO_WLû2Z 2Z +REG11 ìVCC18_IOûw@w@+REG12ìVCC_28û*¹€*¹€+pwm@20030000,rockchip,rk2928-pwm¨ ?äF disabled“default¡pwm@20030010,rockchip,rk2928-pwm¨ ?äFokay“default¡watchdog@2004c000 ,rockchip,rk3188-wdtsnps,dw-wdt¨ ÀäK ³3okaypwm@20050020,rockchip,rk2928-pwm¨  ?äGokay“default¡pwm@20050030,rockchip,rk2928-pwm¨ 0?äGokay“default¡i2c@20056000,rockchip,rk3188-i2c¨ ` ³*üäRëi2c disabled“default¡i2c@2005a000,rockchip,rk3188-i2c¨   ³+üäSëi2c disabled“default¡i2c@2005e000,rockchip,rk3188-i2c¨ à ³4üäTëi2c disabled“default¡ serial@20064000,snps,dw-apb-uart¨ @ ³$|†ëbaudclkapb_pclkäBNokay“default¡!serial@20068000,snps,dw-apb-uart¨ € ³%|†ëbaudclkapb_pclkäCOokay“default¡"saradc@2006c000,rockchip,saradc¨ À ³JäGJësaradcapb_pclk\W csaradc-apb disabledspi@20070000(,rockchip,rk3188-spirockchip,rk3066-spiäEHëspiclkapb_pclk ³&¨ o# # ttxrx disabled“default¡$%&'spi@20074000(,rockchip,rk3188-spirockchip,rk3066-spiäFIëspiclkapb_pclk ³'¨ @o# # ttxrx disabled“default¡()*+cpus~rockchip,rk3066-smpcpu@0œcpu,arm,cortex-a9Œ,¨@‰@™p›@ÐO€Œ0a€g8 s€à˜ 'À~ð°ÀHÂÀ Yø®œ@ä¼-cpu@1œcpu,arm,cortex-a9Œ,¨cpu@2œcpu,arm,cortex-a9Œ,¨cpu@3œcpu,arm,cortex-a9Œ,¨sram@10080000 ,mmio-sram¨€ ¬€smp-sram@0,rockchip,rk3066-smp-sram¨Pi2s@1011a000(,rockchip,rk3188-i2srockchip,rk3066-i2s¨   ³ “default¡.o//ttxrxëi2s_hclki2s_clkäÆKÈã disabledsound@1011e000,,rockchip,rk3188-spdifrockchip,rk3066-spdif¨à ý ëhclkmclkäÅNo/ttx ³ “default¡0okay÷5ý5clock-controller@20000000,rockchip,rk3188-cru¨ ü÷ýefuse@20010000,rockchip,rockchip-efuse¨ @ä[ ëpclk_efusecpu_leakage@17¨phy0,rockchip,rk3188-usb-phyrockchip,rk3288-usb-phyüokayusb-phy@10c¨ äQëphyclk÷ýusb-phy@11c¨äRëphyclk÷ýpinctrl,rockchip,rk3188-pinctrlü&1¬gpio0@2000a000,rockchip,rk3188-gpio-bank0¨   ³6äU3CVk÷ýgpio1@2003c000,rockchip,gpio-bank¨ À ³7äV3CVkgpio2@2003e000,rockchip,gpio-bank¨ à ³8äW3CVk÷8ý8gpio3@20080000,rockchip,gpio-bank¨  ³9äX3CVk÷ ý pcfg_pull_upO÷3ý3pcfg_pull_down\pcfg_pull_nonek÷2ý2emmcemmc-clkx2emmc-cmdx3emmc-rstx2emacemac-xfer€x22222222÷ýemac-mdio x22÷ ý i2c0i2c0-xfer x22÷ýi2c1i2c1-xfer x22÷ýi2c2i2c2-xfer x22÷ýi2c3i2c3-xfer x22÷ýi2c4i2c4-xfer x22÷ ý pwm0pwm0-outx2÷ýpwm1pwm1-outx2÷ýpwm2pwm2-outx2÷ýpwm3pwm3-outx2÷ýspi0spi0-clkx3÷$ý$spi0-cs0x3÷'ý'spi0-txx3÷%ý%spi0-rxx3÷&ý&spi0-cs1x3spi1spi1-clkx3÷(ý(spi1-cs0x3÷+ý+spi1-rxx3÷*ý*spi1-txx3÷)ý)spi1-cs1x3uart0uart0-xfer x32÷ýuart0-ctsx2uart0-rtsx2uart1uart1-xfer x32÷ýuart1-ctsx2uart1-rtsx2uart2uart2-xfer x3 2÷!ý!uart3uart3-xfer x 3 2÷"ý"uart3-ctsx 2uart3-rtsx 2sd0sd0-clkx2÷ýsd0-cmdx2÷ýsd0-cdx2÷ýsd0-wpx 2sd0-pwrx2sd0-bus-width1x2sd0-bus-width4@x2222÷ýsd1sd1-clkx2sd1-cmdx2sd1-cdx2sd1-wpx2sd1-bus-width1x2sd1-bus-width4@x2222i2s0i2s0-bus`x222222÷.ý.spdifspdif-txx2÷0ý0pcfg-output-low†÷4ý4act8846act8846-dvs0-ctlx4÷ýhym8563rtc-intx3÷ýlan8720aphy-intx3÷ ý ir-receiverir-recv-pinx 2÷7ý7usbhost-vbus-drvx2÷:ý:otg-vbus-drvx2÷9ý9gpio-keys ,gpio-keys‘power œ¢t­GPIO Key Power³ÄÒdgpio-leds ,gpio-ledsgreen­rock:green:user1 œ äoffblue­rock:blue:user2 œäoffsleep­rock:red:power œäoffsound,simple-audio-cardòSPDIFsimple-audio-card,dai-link@1cpu 5codec 6spdif-out,linux,spdif-ditý÷6ý6gpio-ir-receiver,gpio-ir-receiver œ “default¡7usb-otg-regulator,regulator-fixed &8“default¡9 ìotg-vbusûLK@LK@++sdmmc-regulator,regulator-fixed ìsdmmc-supplyû2Z 2Z  & =† N÷ýusb-host-regulator,regulator-fixed &“default¡: ìhost-pwrûLK@LK@++vsys-regulator,regulator-fixedìvsysûLK@LK@+÷ý #address-cells#size-cellsinterrupt-parentcompatiblemodelethernet0i2c0i2c1i2c2i2c3i2c4mshc0mshc1mshc2serial0serial1serial2serial3spi0spi1device_typeregrangesinterrupts#dma-cellsarm,pl330-broken-no-flushpclocksclock-nameslinux,phandlestatusclock-frequency#clock-cellsclock-output-namescache-unifiedcache-levelinterrupt-controller#interrupt-cellsreg-shiftreg-io-widthpinctrl-namespinctrl-0dr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeg-use-dmaphysphy-namesrockchip,grfmax-speedphy-modephyphy-supplyfifo-depthnum-slotsvmmc-supplybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpsystem-power-controllervp1-supplyvp2-supplyvp3-supplyvp4-supplyinl1-supplyinl2-supplyinl3-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-on#pwm-cells#io-channel-cellsresetsreset-namesdmasdma-namesenable-methodnext-level-cacheoperating-pointsclock-latencycpu0-supplyrockchip,playback-channelsrockchip,capture-channels#sound-dai-cells#reset-cells#phy-cellsrockchip,pmugpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disablerockchip,pinsoutput-lowautorepeatgpioslinux,codelabellinux,input-typewakeup-sourcedebounce-intervaldefault-statesimple-audio-card,namesound-daienable-active-highgpioregulator-boot-onstartup-delay-usvin-supply