%8"H(" ,Embedded Artists i.MX7ULP COM2ea,imx7ulp-comfsl,imx7ulpaliases=/bus@40800000/gpio@40ae0000C/bus@40800000/gpio@40af0000I/bus@40800000/gpio@40b00000O/bus@40800000/gpio@40b10000U/bus@40800000/i2c@40a40000Z/bus@40800000/i2c@40a50000_/bus@40000000/mmc@40370000d/bus@40000000/mmc@40380000i/bus@40000000/serial@402d0000q/bus@40000000/serial@402e0000y/bus@40800000/serial@40a60000/bus@40800000/serial@40a70000/bus@40000000/usb-phy@40350000cpus cpu@f002arm,cortex-a7cpuinterrupt-controller@400210002arm,cortex-a7-gic@@ clock-rosc 2fixed-clockrosc clock-sosc 2fixed-clockn6sosc clock-sirc 2fixed-clock$sirc clock-firc 2fixed-clocklfirc clock-upll 2fixed-clock8upll bus@40000000 2simple-bus @dma-controller@400800002fsl,imx7ulp-edma@ @!       )dmadmamux05crypto@40240000 2fsl,sec-v4.0 @$ @$5% )aclkipgjr@10002fsl,sec-v4.0-job-ring 6jr@20002fsl,sec-v4.0-job-ring  6serial@402d00002fsl,imx7ulp-lpuart@- 5)ipg<L)cn6xokaydefaultserial@402e00002fsl,imx7ulp-lpuart@. 5)ipg<Lcl xdisabledpwm@402500002fsl,imx7ulp-pwm@%<L)5 xdisabledtpm@402600002fsl,imx7ulp-tpm@& 5%)ipgperusb@403300002fsl,imx7ulp-usbfsl,imx6ul-usb@3 (5xokaydefaultusbmisc@40330200&2fsl,imx7ulp-usbmiscfsl,imx7d-usbmisc@3usb-phy@40350000%2fsl,imx7ulp-usbphyfsl,imx6ul-usbphy@5 '5mmc@40370000#2fsl,imx7ulp-usdhcfsl,imx6sx-usdhc@7 *5%$ )ipgahbper(2Gxokay<LdefaultWemmc@40380000#2fsl,imx7ulp-usdhcfsl,imx6sx-usdhc@8 +5%$ )ipgahbper(2G xdisabledclock-controller@403e00002fsl,imx7ulp-scg1@>5 )roscsoscsircfircupllwatchdog@403d00002fsl,imx7ulp-wdt@= 75<n*(clock-controller@403f00002fsl,imx7ulp-pcc2@?X5%$ )*+m)nic1_bus_clknic1_clkddr_clkapll_pfd2apll_pfd1apll_pfd0upllsosc_bus_clkfirc_bus_clkroscspll_bus_clk<L)clock-controller@404100002fsl,imx7ulp-smc1@A5-)divcorehsrun_divcoreclock-controller@40b300002fsl,imx7ulp-pcc3@X5%$ )*+m)nic1_bus_clknic1_clkddr_clkapll_pfd2apll_pfd1apll_pfd0upllsosc_bus_clkfirc_bus_clkroscspll_bus_clkbus@40800000 2simple-bus @i2c@40a400002fsl,imx7ulp-lpi2c@ $5)ipg<Lcl xdisabledi2c@40a500002fsl,imx7ulp-lpi2c@ %5)ipg<Lcl xdisabledserial@40a600002fsl,imx7ulp-lpuart@  5)ipg<Lcl xdisabledserial@40a700002fsl,imx7ulp-lpuart@ !5)ipg<Lcl xdisabledmemory-controller@40ab0000 2fsl,imx7ulp-mmdcfsl,imx6q-mmdc@5 pinctrl@40ac00002fsl,imx7ulp-iomuxc1@lpuart4grp( HLotg1idgrp48 usdhc0grpCBCCCCCCCCBgpio@40ae0000 2fsl,imx7ulp-gpiofsl,vf610-gpio@@@ 05  )gpioportgpio@40af0000 2fsl,imx7ulp-gpiofsl,vf610-gpio@@@@ 15  )gpioport gpio@40b00000 2fsl,imx7ulp-gpiofsl,vf610-gpio@@@ 25  )gpioport@gpio@40b10000 2fsl,imx7ulp-gpiofsl,vf610-gpio@@@ 35  )gpioport`bus@41080000 2simple-bus Asim@410a30002fsl,imx7ulp-simsysconA 0efuse@410a60002fsl,imx7ulp-ocotpsysconA `@5chosen/bus@40000000/serial@402d0000memory@60000000memory` interrupt-parent#address-cells#size-cellsmodelcompatiblegpio0gpio1gpio2gpio3i2c0i2c1mmc0mmc1serial0serial1serial2serial3usbphy0device_typereg#interrupt-cellsinterrupt-controllerphandleclock-frequencyclock-output-names#clock-cellsranges#dma-cellsdma-channelsinterruptsclock-namesclocksassigned-clocksassigned-clock-parentsassigned-clock-ratesstatuspinctrl-namespinctrl-0#pwm-cellsphysfsl,usbmiscahb-burst-configtx-burst-size-dwordrx-burst-size-dwordsrp-disablehnp-disableadp-disable#index-cells#phy-cellsbus-widthfsl,tuning-start-tapfsl,tuning-stepnon-removableno-1-8-vassigned-clocks-parentstimeout-secfsl,pinsgpio-controller#gpio-cellsgpio-rangesstdout-path