J8(zmqmaker,miqirockchip,rk3288& 7mqmaker MiQialiases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/dwmmc@ff0f0000k/dwmmc@ff0c0000q/dwmmc@ff0d0000w/dwmmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000arm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12'@5< Hcpu@501cpuarm,cortex-a12'@5Hcpu@502cpuarm,cortex-a12'@5Hcpu@503cpuarm,cortex-a12'@5Hcpu-opp-tableoperating-points-v2PHopp-126000000[b opp-216000000[ b opp-312000000[b opp-408000000[Qb opp-600000000[#Fb opp-696000000[)|b~opp-816000000[0,bB@opp-1008000000[<bopp-1200000000[Gbopp-1416000000[TfrbOopp-1512000000[ZJb opp-1608000000[_"bpamba simple-buspdma-controller@ff250000arm,pl330arm,primecell%@w5 apb_pclkHdma-controller@ff600000arm,pl330arm,primecell`@w5 apb_pclk disableddma-controller@ffb20000arm,pl330arm,primecell@w5 apb_pclkHYreserved-memorypdma-unusable@fe000000oscillator fixed-clockn6xin24mH timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H 5 a timerpclkdisplay-subsystemrockchip,display-subsystem dwmmc@ff0c0000rockchip,rk3288-dw-mshc р 5Drvbiuciuciu-driveciu-sample  @#resetokay/9K\nydefault dwmmc@ff0d0000rockchip,rk3288-dw-mshc р 5Eswbiuciuciu-driveciu-sample ! @#reset disableddwmmc@ff0e0000rockchip,rk3288-dw-mshc р 5Ftxbiuciuciu-driveciu-sample "@#reset disableddwmmc@ff0f0000rockchip,rk3288-dw-mshc р 5Guybiuciuciu-driveciu-sample #@#resetokay/9nydefaultsaradc@ff100000rockchip,saradc $5I[saradcapb_pclkW #saradc-apbokayspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi5ARspiclkapb_pclk  txrx ,ydefault disabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi5BSspiclkapb_pclk txrx -ydefault !" disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi5CTspiclkapb_pclktxrx .ydefault#$%& disabledi2c@ff140000rockchip,rk3288-i2c >i2c5Mydefault'okayi2c@ff150000rockchip,rk3288-i2c ?i2c5Oydefault( disabledi2c@ff160000rockchip,rk3288-i2c @i2c5Pydefault)okayi2c@ff170000rockchip,rk3288-i2c Ai2c5Qydefault*okayHoserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 75MUbaudclkapb_pclkydefault+ disabledserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 85NVbaudclkapb_pclkydefault, disabledserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 95OWbaudclkapb_pclkydefault-okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :5PXbaudclkapb_pclkydefault.okayserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;5QYbaudclkapb_pclkydefault/ disabledthermal-zonesreserve_thermal 0cpu_thermald 0tripscpu_alert00p<passiveH1cpu_alert10$<passiveH2cpu_crit0_< criticalcooling-mapsmap0G10Lmap1G20Lgpu_thermald 0tripsgpu_alert00p<passiveH3gpu_crit0_< criticalcooling-mapsmap0G30Ltsadc@ff280000rockchip,rk3288-tsadc( %5HZtsadcapb_pclk #tsadc-apbyinitdefaultsleep4[5e4osokayH0ethernet@ff290000rockchip,rk3288-gmac)macirqeth_wake_irq685fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB #stmmacethok7inputydefault89:;<*rgmii3 I'B@ ^=n0wusb@ff500000 generic-ehciP 5usbhost>usb disabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T 5otghost? usb2-phyokayusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X 5otg peripheral@@ @ usb2-phyokayusb@ff5c0000 generic-ehci\ 5usbhost disabledi2c@ff650000rockchip,rk3288-i2ce <i2c5LydefaultAokaysyr827@40silergy,syr827@vdd_cpu P p#7I,e@zBH syr828@41silergy,syr828Avdd_gpu P p#zBhym8563@51haoyu,hym8563Qxin32kact8846@5aactive-semi,act8846ZydefaultCBBBBBBDregulatorsREG1vcc_ddr#REG2vcc_io2Z 2Z#HREG3vdd_log #REG4vcc_20 #HDREG5 vccio_sd2Z 2Z#HREG6 vdd10_lcdB@ B@#REG7vcca_18w@ w@REG8vcca_332Z 2ZHXREG9vcc_lan2Z 2ZH<REG10vdd_10B@ B@#REG11vcc_18w@ w@#HREG12 vcc18_lcdw@ w@#i2c@ff660000rockchip,rk3288-i2cf =i2c5NydefaultEokaypwm@ff680000rockchip,rk3288-pwmhydefaultF5^pwm disabledpwm@ff680010rockchip,rk3288-pwmhydefaultG5^pwm disabledpwm@ff680020rockchip,rk3288-pwmh ydefaultH5^pwm disabledpwm@ff680030rockchip,rk3288-pwmh0ydefaultI5^pwm disabledbus_intmem@ff700000 mmio-srampppsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsHpower-controller!rockchip,rk3288-power-controllerh H\pd_vio@9 5chgfdehilkj$ JKLMNOPQRpd_hevc@11 5op STpd_video@12 5 Upd_gpu@13 5 VWreboot-modesyscon-reboot-modeRB&RB4RB DRBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruv6PHjk$]#gׄeрxhрxhHsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwH6edp-phyrockchip,rk3288-dp-phy5h24mr disabledHlio-domains"rockchip,rk3288-io-voltage-domainokay}X<usbphyrockchip,rk3288-usb-phyokayusb-phy@320r 5]phyclkH@usb-phy@334r45^phyclkH>usb-phy@348rH5_phyclkH?watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt5p Ookaysound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif hclkmclk5TYtx 6ydefaultZ6 disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s 5YYtxrxi2s_hclki2s_clk5Rydefault[ disabledcypto-controller@ff8a0000rockchip,rk3288-crypto@ 0 5}aclkhclksclkapb_pclk #crypto-rstokayiommu@ff900800rockchip,iommu@ iep_mmu5 aclkiface0 disablediommu@ff914000rockchip,iommu @P isp_mmu5 aclkiface0= disabledrga@ff920000rockchip,rk3288-rga 5jaclkhclksclkX\ ilm #coreaxiahbvop@ff930000rockchip,rk3288-vop 5aclk_vopdclk_vophclk_vopX\ def #axiahbdclkf]okayportH endpoint@0m^Hpendpoint@1m_Hmendpoint@2m`Hgendpoint@3maHjiommu@ff930300rockchip,iommu  vopb_mmu5 aclkifaceX\ 0okayH]vop@ff940000rockchip,rk3288-vop 5aclk_vopdclk_vophclk_vopX\  #axiahbdclkfbokayportH endpoint@0mcHqendpoint@1mdHnendpoint@2meHhendpoint@3mfHkiommu@ff940300rockchip,iommu  vopl_mmu5 aclkifaceX\ 0okayHbmipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ 5~d refpclkX\ 6 disabledportsportendpoint@0mgH`endpoint@1mhHelvds@ff96c000rockchip,rk3288-lvds@5g pclk_lvdsylcdciX\ 6 disabledportsport@0endpoint@0mjHaendpoint@1mkHfdp@ff970000rockchip,rk3288-dp@ b5icdppclkldpo#dp6 disabledportsport@0endpoint@0mmH_endpoint@1mnHdhdmi@ff980000rockchip,rk3288-dw-hdmi6 g5hmniahbisfrcecX\ okay}oportsportendpoint@0mpH^endpoint@1mqHcvideo-codec@ff9a0000rockchip,rk3288-vpu   vepuvdpu5 aclkhclkfrX\ iommu@ff9a0800rockchip,iommu vpu_mmu5 aclkiface0X\ Hriommu@ff9c0440rockchip,iommu @@@ o hevc_mmu5 aclkiface0 disabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760$ jobmmugpu5sX\  disabledgpu-opp-tableoperating-points-v2Hsopp@100000000[b~opp@200000000[ b~opp@300000000[bB@opp@400000000[ׄbopp@500000000[ebOopp@600000000[#Fbqos@ffaa0000syscon HVqos@ffaa0080syscon HWqos@ffad0000syscon HKqos@ffad0100syscon HLqos@ffad0180syscon HMqos@ffad0400syscon HNqos@ffad0480syscon HOqos@ffad0500syscon HJqos@ffad0800syscon HPqos@ffad0880syscon HQqos@ffad0900syscon HRqos@ffae0000syscon HUqos@ffaf0000syscon HSqos@ffaf0080syscon HTinterrupt-controller@ffc01000 arm,gic-400@ @ `   Hefuse@ffb40000rockchip,rk3288-efuse 5q pclk_efusecpu_leakage@17pinctrlrockchip,rk3288-pinctrl6pgpio0@ff750000rockchip,gpio-banku Q5@H|gpio1@ff780000rockchip,gpio-bankx R5Agpio2@ff790000rockchip,gpio-banky S5Bgpio3@ff7a0000rockchip,gpio-bankz T5Cgpio4@ff7b0000rockchip,gpio-bank{ U5DH=gpio5@ff7c0000rockchip,gpio-bank| V5Egpio6@ff7d0000rockchip,gpio-bank} W5Fgpio7@ff7e0000rockchip,gpio-bank~ X5GH{gpio8@ff7f0000rockchip,gpio-bank Y5Hhdmihdmi-cec-c0thdmi-cec-c7thdmi-ddc ttpcfg-pull-upHupcfg-pull-downHvpcfg-pull-noneHtpcfg-pull-none-12ma Hwsleepglobal-pwrofftddrio-pwrofftddr0-retentionuddr1-retentionuedpedp-hpd vi2c0i2c0-xfer ttHAi2c1i2c1-xfer ttH'i2c2i2c2-xfer  t tHEi2c3i2c3-xfer ttH(i2c4i2c4-xfer ttH)i2c5i2c5-xfer ttH*i2s0i2s0-bus`ttttttH[lcdclcdc-ctl@ttttHisdmmcsdmmc-clkwH sdmmc-cmdxHsdmmc-cduHsdmmc-bus1usdmmc-bus4@xxxxHsdmmc-pwr tH~sdio0sdio0-bus1usdio0-bus4@uuuusdio0-cmdusdio0-clktsdio0-cdusdio0-wpusdio0-pwrusdio0-bkpwrusdio0-intusdio1sdio1-bus1usdio1-bus4@uuuusdio1-cdusdio1-wpusdio1-bkpwrusdio1-intusdio1-cmdusdio1-clktsdio1-pwr uemmcemmc-clktHemmc-cmduHemmc-pwr uHemmc-bus1uemmc-bus4@uuuuemmc-bus8uuuuuuuuHspi0spi0-clk uHspi0-cs0 uHspi0-txuHspi0-rxuHspi0-cs1uspi1spi1-clk uHspi1-cs0 uH"spi1-rxuH!spi1-txuH spi2spi2-cs1uspi2-clkuH#spi2-cs0uH&spi2-rxuH%spi2-tx uH$uart0uart0-xfer utH+uart0-ctsuuart0-rtstuart1uart1-xfer u tH,uart1-cts uuart1-rts tuart2uart2-xfer utH-uart3uart3-xfer utH.uart3-cts uuart3-rts tuart4uart4-xfer utH/uart4-cts uuart4-rts ttsadcotp-gpio tH4otp-out tH5pwm0pwm0-pintHFpwm1pwm1-pintHGpwm2pwm2-pintHHpwm3pwm3-pintHIgmacrgmii-pinsttttwwwwttt wwttH8rmii-pinsttttttttttphy-int uH;phy-pmebuH:phy-rstyH9spdifspdif-tx tHZpcfg-output-highHypcfg-output-lowHzpcfg-pull-up-drv-12ma Hxact8846pmic-intupmic-sleepzpmic-vselzHCusb_hosthost-vbus-drvtH}chosen(serial2:115200n8memory@0memoryexternal-gmac-clock fixed-clocksY@ ext_gmacH7leds gpio-ledswork 4{:miqi:green:user@timerflash-regulatorregulator-fixed vcc_flashw@ w@zHusb-host-regulatorregulator-fixedV i|ydefault} vcc_hostLK@ LK@#zBsdmmc-regulatorregulator-fixed i{ ydefault~vcc_sd2Z 2ZizHvsys-regulatorregulator-fixedvcc_sysLK@ LK@#7HB #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclockscpu0-supplyphandleopp-sharedopp-hzopp-microvoltranges#dma-cellsarm,pl330-broken-no-flushpclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredportsmax-frequencyfifo-depthreset-namesbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaydisable-wppinctrl-namespinctrl-0vmmc-supplyvqmmc-supplynon-removable#io-channel-cellsvref-supplydmasdma-namesreg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfassigned-clocksassigned-clock-parentsclock_in_outphy-supplyphy-modesnps,reset-active-lowsnps,reset-delays-ussnps,reset-gpiotx_delayrx_delayphysphy-namesdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizefcs,suspend-voltage-selectorregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onregulator-enable-ramp-delayregulator-ramp-delayvin-supplysystem-power-controllervp1-supplyvp2-supplyvp3-supplyvp4-supplyinl1-supplyinl2-supplyinl3-supply#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsaudio-supplyflash0-supplyflash1-supplygpio30-supplygpio1830-supplylcdc-supplysdcard-supplywifi-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointddc-i2c-businterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowstdout-pathgpioslabellinux,default-triggerenable-active-highstartup-delay-us