V"8Q(P(,haoyu,marsboard-rk3066rockchip,rk3066a7MarsBoard RK3066aliases=/ethernet@10204000G/i2c@2002d000L/i2c@2002f000Q/i2c@20056000V/i2c@2005a000[/i2c@2005e000`/dwmmc@1021c000f/dwmmc@10214000l/dwmmc@10218000r/serial@10124000z/serial@10126000/serial@20064000/serial@20068000/spi@20070000/spi@20074000amba ,simple-busdma-controller@20018000,arm,pl330arm,primecell @ apb_pclkdma-controller@2001c000,arm,pl330arm,primecell @ apb_pclk disableddma-controller@20078000,arm,pl330arm,primecell @ apb_pclkoscillator ,fixed-clockn6 xin24mgpu@10090000",rockchip,rk3066-maliarm,mali-400  corebus*:Ox disabledx5Vgpgpmmupp0ppmmu0pp1ppmmu1pp2ppmmu2pp3ppmmu3fl2-cache-controller@10138000,arm,pl310-cachet8scu@1013c000,arm,cortex-a9-scuglobal-timer@1013c200,arm,cortex-a9-global-timer   local-timer@1013c600,arm,cortex-a9-twd-timer   interrupt-controller@1013d000,arm,cortex-a9-gicserial@10124000&,rockchip,rk3066-uartsnps,dw-apb-uart@ "baudclkapb_pclk@Lokaytxrxdefaultserial@10126000&,rockchip,rk3066-uartsnps,dw-apb-uart` #baudclkapb_pclkAMokaytxrxdefaultqos@1012d000,syscon !qos@1012e000,syscon  qos@1012f000,syscon qos@1012f080,syscon qos@1012f100,syscon qos@1012f180,syscon qos@1012f200,syscon qos@1012f280,syscon usb@10180000,rockchip,rk3066-usbsnps,dwc2 otgotg @@ * /usb2-phyokayusb@101c0000 ,snps,dwc2 otghost* /usb2-phyokayethernet@10204000,rockchip,rk3066-emac @< 9 D hclkmacrefFdPrmiiokayY ] default  ethernet-phy@0 dwmmc@10214000,rockchip,rk2928-dw-mshc!@ Hbiuciurx-txhOQsresetokaydefaultdwmmc@10218000,rockchip,rk2928-dw-mshc! Ibiuciurx-txhORsreset disableddefaultdwmmc@1021c000,rockchip,rk2928-dw-mshc! Jbiuciurx-txhOSsreset disabledpmu@20004000&,rockchip,rk3066-pmusysconsimple-mfd @reboot-mode,syscon-reboot-mode@RBRBRB RBpower-controller!,rockchip,rk3066-power-controllerpd_vio@7POpd_video@6  pd_gpu@8!grf@20008000,syscon  i2c@2002d000,rockchip,rk3066-i2c  (9 i2cP disableddefault"i2c@2002f000,rockchip,rk3066-i2c  )9 Qi2cokaydefault#tps@2d-$%% %%!&-&9%E% ,ti,tps65910regulatorsregulator@0Rvcc_rtcauvrtcregulator@1Rvcc_ioauvio&regulator@2Rvdd_arm '`auvdd19regulator@3Rvcc_ddr '`auvdd2regulator@5 Rvcc18_cifauvdig1regulator@6Rvdd_11auvdig2regulator@7Rvcc_25auvpllregulator@8Rvcc_18auvdacregulator@9 Rvcc25_hdmia uvaux1regulator@10Rvcca_33a uvaux2regulator@11 Rvcc_rmii uvaux33 regulator@12 Rvcc28_cifa uvmmcregulator@4uvdd3regulator@13 uvbbpwm@20030000,rockchip,rk2928-pwm F disableddefault'pwm@20030010,rockchip,rk2928-pwm F disableddefault(watchdog@2004c000 ,rockchip,rk3066-wdtsnps,dw-wdt K 3okaypwm@20050020,rockchip,rk2928-pwm  G disableddefault)pwm@20050030,rockchip,rk2928-pwm 0Gokaydefault*?i2c@20056000,rockchip,rk3066-i2c ` *9 Ri2c disableddefault+i2c@2005a000,rockchip,rk3066-i2c  +9 Si2c disableddefault,i2c@2005e000,rockchip,rk3066-i2c  49 Ti2c disableddefault-serial@20064000&,rockchip,rk3066-uartsnps,dw-apb-uart @ $baudclkapb_pclkBNokaytxrxdefault.serial@20068000&,rockchip,rk3066-uartsnps,dw-apb-uart  %baudclkapb_pclkCOokay txrxdefault/saradc@2006c000,rockchip,saradc  GJsaradcapb_pclkOW ssaradc-apb disabledspi@20070000,rockchip,rk3066-spiEHspiclkapb_pclk &   txrx disableddefault0123spi@20074000,rockchip,rk3066-spiFIspiclkapb_pclk ' @  txrx disableddefault4567cpusrockchip,rk3066-smpcpu@0cpu,arm,cortex-a988@ Oa* s* 'g8%@39cpu@1cpu,arm,cortex-a98sram@10080000 ,mmio-sram smp-sram@0,rockchip,rk3066-smp-sramPi2s@10118000,rockchip,rk3066-i2s  default:txrxi2s_hclki2s_clkK?Zt disabledi2s@1011a000,rockchip,rk3066-i2s  default;txrxi2s_hclki2s_clkL?Zt disabledi2s@1011c000,rockchip,rk3066-i2s  default<  txrxi2s_hclki2s_clkM?Zt disabledclock-controller@20000000,rockchip,rk3066a-cru 9  @*^_ :ׄ#gрxhрxhtimer@2000e000,snps,dw-apb-timer-osc  .VD timerpclkefuse@20010000,rockchip,rk3066a-efuse @[ pclk_efusecpu_leakage@17timer@20038000,snps,dw-apb-timer-osc  ,TB timerpclktimer@2003a000,snps,dw-apb-timer-osc  -UC timerpclktsadc@20060000,rockchip,rk3066-tsadc ]]saradcapb_pclk O\ ssaradc-apb disabledphy1,rockchip,rk3066a-usb-phyrockchip,rk3288-usb-phy9 okayusb-phy@17c|Qphyclk usb-phy@188Rphyclk pinctrl,rockchip,rk3066a-pinctrl9 gpio0@20034000,rockchip,gpio-bank @ 6Ugpio1@2003c000,rockchip,gpio-bank  7Vgpio2@2003e000,rockchip,gpio-bank  8Wgpio3@20080000,rockchip,gpio-bank  9X@gpio4@20084000,rockchip,gpio-bank @ :Ygpio6@2000a000,rockchip,gpio-bank  <Z$pcfg_pull_default>pcfg_pull_none=emacemac-xfer======== emac-mdio == emmcemmc-clk>emmc-cmd >emmc-rst >i2c0i2c0-xfer =="i2c1i2c1-xfer ==#i2c2i2c2-xfer ==+i2c3i2c3-xfer ==,i2c4i2c4-xfer ==-pwm0pwm0-out='pwm1pwm1-out=(pwm2pwm2-out=)pwm3pwm3-out=*spi0spi0-clk>0spi0-cs0>3spi0-tx>1spi0-rx>2spi0-cs1>spi1spi1-clk>4spi1-cs0>7spi1-rx>6spi1-tx>5spi1-cs1>uart0uart0-xfer >>uart0-cts>uart0-rts>uart1uart1-xfer >>uart1-cts>uart1-rts>uart2uart2-xfer > >.uart3uart3-xfer >>/uart3-cts>uart3-rts>sd0sd0-clk>sd0-cmd >sd0-cd>sd0-wp>sd0-bus-width1 >sd0-bus-width4@ > > > >sd1sd1-clk>sd1-cmd>sd1-cd>sd1-wp>sd1-bus-width1>sd1-bus-width4@>>>>i2s0i2s0-bus>> > > > > >>>:i2s1i2s1-bus`>>>>>>;i2s2i2s2-bus`>>>>>><lan8720aphy-int=memory@60000000memory`@vdd-log,pwm-regulator ?Rvdd_logOOaB@dO*okaysdmmc-regulator,regulator-fixed Rsdmmc-supply-- @&vsys-regulator,regulator-fixedRvsysLK@LK@% #address-cells#size-cellsinterrupt-parentcompatiblemodelethernet0i2c0i2c1i2c2i2c3i2c4mshc0mshc1mshc2serial0serial1serial2serial3spi0spi1rangesreginterrupts#dma-cellsarm,pl330-broken-no-flushpclocksclock-namesphandlestatusclock-frequency#clock-cellsclock-output-namesassigned-clocksassigned-clock-ratesresetsinterrupt-namespower-domainscache-unifiedcache-levelinterrupt-controller#interrupt-cellsreg-shiftreg-io-widthdmasdma-namespinctrl-namespinctrl-0dr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesrockchip,grfmax-speedphy-modephyphy-supplyfifo-depthreset-namesmax-frequencyvmmc-supplyoffsetmode-normalmode-recoverymode-bootloadermode-loader#power-domain-cellspm_qosvcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvccio-supplyregulator-nameregulator-always-onregulator-compatibleregulator-min-microvoltregulator-max-microvoltregulator-boot-on#pwm-cells#io-channel-cellsenable-methoddevice_typenext-level-cacheoperating-pointsclock-latencycpu0-supplyrockchip,playback-channelsrockchip,capture-channels#sound-dai-cells#reset-cells#phy-cellsgpio-controller#gpio-cellsbias-pull-pin-defaultbias-disablerockchip,pinspwmsvoltage-tablegpiostartup-delay-usvin-supply