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#    ***** GENERATED FILE -- DO NOT EDIT! *****
#    ***** GENERATED FILE -- DO NOT EDIT! *****
#    ***** GENERATED FILE -- DO NOT EDIT! *****
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EVEX_INSTRUCTIONS()::
# EMITTING VMOVRSB (VMOVRSB-128-1)
{
ICLASS:      VMOVRSB
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_MOVRS_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_FULLMEM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x6F VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 W0 VL128 mode64 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u8
IFORM:       VMOVRSB_XMMu8_MASKmskw_MEMu8_AVX512
}


# EMITTING VMOVRSB (VMOVRSB-256-1)
{
ICLASS:      VMOVRSB
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_MOVRS_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_FULLMEM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x6F VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 W0 VL256 mode64 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u8
IFORM:       VMOVRSB_YMMu8_MASKmskw_MEMu8_AVX512
}


# EMITTING VMOVRSB (VMOVRSB-512-1)
{
ICLASS:      VMOVRSB
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_MOVRS_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_FULLMEM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x6F VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 W0 VL512 mode64 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u8
IFORM:       VMOVRSB_ZMMu8_MASKmskw_MEMu8_AVX512
}


# EMITTING VMOVRSD (VMOVRSD-128-1)
{
ICLASS:      VMOVRSD
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_MOVRS_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_FULLMEM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x6F VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 W0 VL128 mode64 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32
IFORM:       VMOVRSD_XMMu32_MASKmskw_MEMu32_AVX512
}


# EMITTING VMOVRSD (VMOVRSD-256-1)
{
ICLASS:      VMOVRSD
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_MOVRS_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_FULLMEM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x6F VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 W0 VL256 mode64 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u32
IFORM:       VMOVRSD_YMMu32_MASKmskw_MEMu32_AVX512
}


# EMITTING VMOVRSD (VMOVRSD-512-1)
{
ICLASS:      VMOVRSD
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_MOVRS_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_FULLMEM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x6F VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 W0 VL512 mode64 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u32
IFORM:       VMOVRSD_ZMMu32_MASKmskw_MEMu32_AVX512
}


# EMITTING VMOVRSQ (VMOVRSQ-128-1)
{
ICLASS:      VMOVRSQ
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_MOVRS_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_FULLMEM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x6F VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 W1 VL128 mode64 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64
IFORM:       VMOVRSQ_XMMu64_MASKmskw_MEMu64_AVX512
}


# EMITTING VMOVRSQ (VMOVRSQ-256-1)
{
ICLASS:      VMOVRSQ
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_MOVRS_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_FULLMEM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x6F VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 W1 VL256 mode64 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u64
IFORM:       VMOVRSQ_YMMu64_MASKmskw_MEMu64_AVX512
}


# EMITTING VMOVRSQ (VMOVRSQ-512-1)
{
ICLASS:      VMOVRSQ
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_MOVRS_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_FULLMEM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x6F VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 W1 VL512 mode64 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u64
IFORM:       VMOVRSQ_ZMMu64_MASKmskw_MEMu64_AVX512
}


# EMITTING VMOVRSW (VMOVRSW-128-1)
{
ICLASS:      VMOVRSW
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_MOVRS_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_FULLMEM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x6F VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 W1 VL128 mode64 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16
IFORM:       VMOVRSW_XMMu16_MASKmskw_MEMu16_AVX512
}


# EMITTING VMOVRSW (VMOVRSW-256-1)
{
ICLASS:      VMOVRSW
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_MOVRS_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_FULLMEM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x6F VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 W1 VL256 mode64 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16
IFORM:       VMOVRSW_YMMu16_MASKmskw_MEMu16_AVX512
}


# EMITTING VMOVRSW (VMOVRSW-512-1)
{
ICLASS:      VMOVRSW
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_MOVRS_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_FULLMEM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x6F VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 W1 VL512 mode64 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16
IFORM:       VMOVRSW_ZMMu16_MASKmskw_MEMu16_AVX512
}


INSTRUCTIONS()::
# EMITTING MOVRS (MOVRS-N/A-1)
{
ICLASS:      MOVRS
CPL:         3
CATEGORY:    LEGACY
EXTENSION:   MOVRS
ISA_SET:     MOVRS
EXCEPTIONS:  LEGACY-MOVRS
REAL_OPCODE: Y
PATTERN:     0x0F 0x38 0x8B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() norep mode64
OPERANDS:    REG0=GPRv_R():w:v MEM0:r:v
IFORM:       MOVRS_GPRv_MEMv
}


# EMITTING MOVRS (MOVRS-N/A-2)
{
ICLASS:      MOVRS
CPL:         3
CATEGORY:    LEGACY
EXTENSION:   MOVRS
ISA_SET:     MOVRS
EXCEPTIONS:  LEGACY-MOVRS
REAL_OPCODE: Y
ATTRIBUTES:  BYTEOP 
PATTERN:     0x0F 0x38 0x8A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() norep mode64
OPERANDS:    REG0=GPR8_R():w:b:i8 MEM0:r:b:i8
IFORM:       MOVRS_GPR8i8_MEMi8
}


# EMITTING PREFETCHRST2 (PREFETCHRST2-N/A-1)
{
ICLASS:      PREFETCHRST2
CPL:         3
CATEGORY:    PREFETCH
EXTENSION:   MOVRS
ISA_SET:     MOVRS
EXCEPTIONS:  LEGACY-PREFETCH
REAL_OPCODE: Y
ATTRIBUTES:  PREFETCH 
PATTERN:     0x0F 0x18 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() PREFETCHRST=1
OPERANDS:    MEM0:r:mprefetch
IFORM:       PREFETCHRST2_MEMu8
}


